Digital signal processing apparatus, such as interface circuits for data storage disk drives or integrated memory circuits frequently require the capability of executing signal processing operations with highly accurate timing, irrespective of the frequency and time of occurrence of a basic system clock that controls the majority of events within a system. Attempting to generate a timing signal asynchronously with respect to the system clock by using multiple occurrences of the clock signal is not necessarily precise, or even possible. This is so particularly where the initiation point of the timing signal is selected at a time that falls immediately subsequent to a transition in the system clock. For example, in a data processing system operating off a precision 20 MHz crystal reference, clock signals occur at intervals of 50 ns. By simply counting five consecutive clock signals one could ostensibly generate a 250 ns. delay pulse. However, if the clock count begins at a time which is slightly subsequent to the most recent clock signals (e.g. 1 ns. later), then the actual time of occurrence of a transition edge of the intended 250 ns. pulse may be retarded by nearly one clock cycle (49 ns. in the example). Because of this inherent uncertainty window in using a fixed system clock, it is common practice to achieve a desired delay using "trimmable" components. Such delay techniques may be in the form of RC delay circuits, monostable multivibrators (one-shots), and precision delay lines. Unfortunately, within a given circuit architecture, the insertion of individual delay components cannot always be readily accomplished and often requires the use of a separate "off-chip" timing circuit. This not only increases hardware complexity, but is subject to drift. Precision delay lines are not subject to the drift problem. However, they add considerable cost and, consequently, are most practically employed in "higher ticket" items such as memories.
With reference to teachings in the field of variable delay signal generating circuits the following art may be considered.
Reference is made to W. J. Stewart U.S. Pat. No. 4,868,430, entitled "Self-Correcting Digitally Controlled Timing Circuit". Stewart discloses a digitally controlled timing circuit for providing an output pulse signal precisely delayed with respect to an input signal irrespective of the time of occurrence of a system clock, but which uses the precision of the system clock to self-correct any inaccuracy in delay. The circuit includes a plurality of delay elements, the delay period of a respective one of which is adjustable, coupled between an input terminal, to which an input terminal is applied, and an output terminal from which a delayed output signal is to be derived.
Stewart teaches how to hard-wire a plurality of digital components to provide a number of pulses within a fixed timing window. If a different number of pulses is desired within the same timing window, reworking of the hardware would be required to conform to the new number of pulses. This could prove costly, time consuming and error prone.
Reference is made to M. C. Swapp U.S. Pat. No. 4,745,310, entitled "Programmable Delay Circuit" which describes a monolithic integrated delay circuit that comprises a gate coupled for receiving a digital input signal. The output of the gate is capacitively loaded whereby the output signal has a sloping downward transition. A line receiver has a first input coupled to the gate and a second input coupled for receiving an analog signal for comparing the analog signal with the output of the gate and for providing a digital signal that is delayed with respect to the input digital signal.
Swapp discloses a programmable delay circuit that combines analog and digital components. Combining analog with digital components has the disadvantage of making more difficult the task of verifying the design through simulation and of automatically testing the complete circuit. Therefore, a purely digital design is preferred in that it can be arrived at quickly by using standard cells which are readily available and which require no special tuning, as would be the case of analog components.
Other U.S. patents are cited hereinafter for reference only to show existing techniques in the art of delaying signals with respect to one another.
Reference is made to Kenji Yoshida U.S. Pat. No. 4,504,749 entitled "Delay Pulse Generating Circuit", whereby a delay signal generating circuit includes feedback loops and components for selectively setting the delay time of a delay unit in one of the loops. The circuit is used to provide an adjustable delay to a signal being propogated therethrough, such that the delay unit can be bypassed.
Reference is made to I. P. Flora et al U.S. Pat. No. 4,755,704, entitled "Automatic Clock De-Skewing Apparatus", which provides a plurality of circuit boards of a data processing system. Each circuit board is of multi-layer construction and contains a clock distribution chip which includes on-chip automatic clock de-skewing circuitry for providing de-skewed clocks to other chips on the circuit board.
Reference is made to J. Hullwegen U.S. Pat. No. 4,524,448, entitled "Variable Delay Unit For Data Synchronizer Using Phase-Sensitive Counter to Vary the Delay". Hullwegen describes a signal processing circuit for a signal varying in its properties, e.g., in its degrees of distortion. There, the input signal is fed in parallel to two similar processing circuits, e.g., equalizers, the characteristics of which can be varied by a control signal, such that the control signal of one processing circuit is periodically varied and the output is fed to a detector circuit capable of emitting a trigger pulse to a holding circuit which stores the control signal level to be fed to another processing circuit. A variable delay unit for data is controlled by a continually varying up-down counter, the contents of which continuously vary at the rate of a high frequency clock pulse.
Reference is made to E. Berndlmaier U.S. Pat. No. 4,346,343, entitled "Power Control Means For Eliminating Circuit to Circuit Delay Differences and Providing A Desired Circuit Delay". It describes an on-chip delay regulator circuit which varies the power in logic or array circuits on the same chip so as to eliminate or to minimize chip-to-chip circuit differences caused by power supply variations, lot to lot process differences, temperature, etc. The on-chip delay regulator accomplishes this by comparing a reference signal to an on-chip generated signal which is sensitive to power supply changes, etc. This comparison creates an error signal which is used to change the power supplied to the on-chip circuits.
Reference is made to European Patent Application 0 306 662 to H. J. Greub, entitled "Apparatus For Skew Compensating Signals", which describes a clock signal that is transmitted to the nodes of each of several interconnected synchronous integrated circuits through separate adjustable delay circuits, and such that the time delay of each delay circuit is adjusted so that the clock signal arrives at each node at the same time, thus synchronizing the operation of the separate integrated circuits with one another. Each delay circuit comprises a set of signal delay elements which can be selectively switched into the clock path so that the clock delay signal delay may be adjusted by adjusting the number of signal delay elements in the clock signal path.
Reference is made to UK Patent Application GB 2 040 628 A to A. A. Vacca, entitled "A Clock Pulse Circuit", whereby a clock network for LSI chips of a data handling network comprises a pulse producing circuit on each LSI chip responsive to the leading edge of a master clock signal to produce local clock signals whose pulse durations are dependent at least in part on the manufacturing and environmental conditions of the LSI chip. The pulse producing circuit on each LSI chip consists of a plurality of delay networks and a NOR gate so arranged that the gate is set to produce the leading edges of the local clock pulse coincident with the leading edge of the master clock pulse, and will produce the trailing edge of the local clock pulse upon a delay dependent, at least in part, upon the manufacturing conditions employed in the fabrication of the chip and the environmental conditions to which the chip is subjected.